Due to the high degree of integration of modem sequential circuits, the test and the diagnostic analysis of such circuits requires great effort. In the test of electronic test circuits, test patterns are usually applied to the input contacts of the circuits to be tested and the test responses of the circuits are analyzed.
In this context, it is conceivable to combine or to compact, respectively, the test responses of the circuits to be tested in a multi-input signature register to form a signature. The signature thus obtained is compared with the error-free signature, for example previously obtained by means of a simulation, in the tester used for testing such integrated circuits. When the two signatures match, the integrated circuit is free of errors. If the two signatures differ, the tested circuit is faulty.
If an integrated circuit is identified as faulty during such a test, it is expensive and time-consuming to accurately locate the faulty memory cells or the faulty elements of this integrated circuit. To identify the faulty memory cells or the faulty circuit elements, respectively, often time-consuming and costly 100% tests must therefore be performed by diagnostic analysis following such combinational test methods.
For these and other reasons, there is a need for the present invention.